This invention relates to electronic design automation, specifically to verification of electronic circuit designs' functional correctness using a computer program.
Electronic circuit designs have become very complex as VLSI technologies allow larger and larger chips. The cost of design mistakes gets higher and the chance of making mistakes also gets higher as VLSI chips get more and more complex. The complexity of functional verification has been so high that no modern VLSI design project can afford complete verification. All such projects do just as much verification as possible. They all need to reduce the verification complexity so that they can verify more with the resource limitation.
Simulation is the most efficient method to verify a feature of a VLSI design a bit: with one test case or a small number of test cases. However, simulation cannot go much beyond such a bit of verification due to the complexity. Some methods are better than simulation overall but they cannot get beyond certain levels of verification, either. There is a need to combine these methods and to use each only in the part that it is best at.
Simulation's efficiency is low when verifying unexpected interference. In a large design, a feature typically involves a small part of the logic at any time while the other parts are idle or used for other purposes at the same time. Unexpected participation of these other parts hurts this feature's functional correctness, and it has too many possibilities so that there is no way for simulation to check all or a good portion of these possibilities. There is no previously known method that just focuses on such unexpected interference or unexpected participation of supposedly irrelevant logic.
A special kind of unexpected interference is in the relevant logic. Control values in the relevant logic determines how other signals (including data values) are processed, but each data value is not supposed to determine how other data values are processed. Simulation can detect such problems with unexpected interference between data values, but it is not very productive. Therefore, as the data amount get larger, people give up on checking unexpected interference between data values with simulation. Such unexpected interference between data values causes functional mistakes, but it takes too much simulation effort to examine such issues thoroughly.
A verification plan typically defines how to use simulation (and possibly other methods) to verify the features of a VLSI design. An important part of the verification plan is the collection of test cases to use. The test cases in a flawed verification plan can be not enough or more than enough. The goal of reducing the verification complexity is to determine what test cases are just enough in a verification plan. If the verification plan includes functional coverage, the test cases in the verification plan are indirectly specified through the functional coverage goal. Then the goal of reducing the verification complexity is to determine whether the functional coverage goal is just enough.